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A well-written charter establishes clear objectives, definitions, and guidelines, aligning group members and the broader RISC-V Community from the start. It defines purpose, scope, and accountability, preventing confusion and scope creep, and serves as a reference to keep the group focused and efficient. |
Introduction
Definitions (Optional)
Background
Objectives
Exclusions (Optional)
Collaborations
For more details, refer to the list of active work groups and committeesCovert channels are communication channels that are not intended to transfer information. Timing channels are covert channels that exploit physical sharing in microarchitectural resources, such as caches, buffers, and branch predictors. For instance, timing channels can be used to extract secrets as part of a microarchitectural speculation attack such as Spectre-like attacks.
To prevent timing channels, shared hardware resources must be strictly partitioned between isolated applications. The Timing Fences Task Group will propose a small ISA extension to enable such partitioning of shared microarchitectural state. For instance, we will introduce a temporal fence instruction which can be used to temporally partition shared on-core microarchitectural state by clearing it, e.g., when switching between isolated applications.
The proposed RISC-V Timing Fences TG will collaborate to produce:
A small ISA extension (possibly no more than one or two instructions, or only a new CSR).
A non-normative short guide: defining threat models, developing rationale, programming model, etc.
A proof-of-concept implementation, including both a prototype RISC-V core and compiler that manages the necessary intrinsics.
A test strategy guide, including a test suite for common covert channels.
The Sail model corresponding to this extension.
The TG will work with the appropriate Priv/Unpriv ISA committee, Architecture Review Committee, and Security HC.
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