This page gives an overview of upstream projects. If you miss information or find mistakes, please edit.

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There are multiple RISC-V ports of xv6, including one for the xv6 (https://pdos.csail.mit.edu/6.828/2022/xv6.html).

• Generic: https://github.com/mit-pdos/xv6-riscv
• Book: https://github.com/mit-pdos/xv6-riscv-book

Ports

• iCE40 FPGA https://gitlab.com/x653/xv6-riscv-fpga
• Allwinner D1: https://github.com/michaelengel/xv6-d1
• JH7110 (VisionFive 2): https://github.com/michaelengel/xv6-vf2

Zephyr

RISC-V Maintainers

• Karol Gugala (Antmicro)
• Tomasz Gorochowik (Antmicro)
• Filip Kokosinski (Antmicro)

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