Date
Disclosures
| Expand | ||
|---|---|---|
| ||
Participants
| Expand | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||
|
Presentations
Title | Presenter | File | |
|---|---|---|---|
| 1 | |||
| 2 |
Notes & Action Items
Board Updates:
Beagle - blog
SiFive - press
StarFive
How How The Ubuntu Linux Performance Has Evolved For SiFive Over the Last Four Years - link
StarFive
RIOS - news
Allwinner
Microchip - news
SpacemiT - news
Microsemi
Milk-V - announcements
Running Deepseek R1 Distill with llama.cpp on Milk-V Pioneer Box - link
...
AlmaLinux
Arch Linux
Alpine Linux
FreeBSD
OpenEuler
Debian
Gentoo (Dev Images) link
Fedora
SUSE
For SUSE, we're experimenting with integrating the Pioneer boxes into our build service/system infrastructure instead of QEMU on x86_64.
Canonical
Android (AOSP)
seL4
NixOS
R9
oreboot
We got Linux to boot on the K230
Turns out, the "debug register" for the timer was really the normal timer control register after all (STC = System Timer Clock), I just mixed up the columns in the manual again; though the explanation there is still confusing and inconsistent and it doesn't say anything about being related to the mtimer (RISC-V platform timer)
Had to add some more helpers, now have shared libraries for XuanTie and RISC-V
Did another Twitch live development stream, started a new series with the K230: https://www.youtube.com/watch?v=hfz8QBB4M3g
We are cleaning up a lot in oreboot
Ripped out tarpaulin (test coverage report)
Removed obsolete Makefiles and targets
Upgraded to Rust nightly 2025-03-01
Discussed compression in oreboot, we'll switch to miniz_oxide
Firmware
Managarm
Linux Kernel
RISC-V
Developer Board Status
Developer Experience15 Minute Demos?
Running SAIL/ACT Tests on RISC-V Hardware?
Ecosystem Lab Partners
EPCC has provided a one pager to get access to their hardware, interested in getting more people access to their platform.
...
The RISC-V Architecture: 16 Boards and MCUs You Should Know - link
Alibaba launching server-grade RISC-V CPU - link
The Role of RISC-V in Shaping the Future - link
blog on running swupdate on licheepi 4a:
https://kanakshilledar.github.io/2025-03-06/licheepi-4a-swupdate
There was a Tenstorrent talk about their Ascalon processor and their future high perf CPU plans: https://riscv.or.jp/wp-content/uploads/Japan_RISC-V_day_Spring_2025_compressed.pdf
In the presentation, it was mentioned that they plan to release a devboard and laptop of their Athena chiplet with 8x Ascalon cores, presumably next year: https://youtu.be/ttQtC1dQqwo?t=1035 (timestamp)
Miscellaneous notes:
Meeting about some random Deepseek experiences (including MV Pioneer) in 2 weeks…. https://blu.org/
OrangePi just announced a RISC-V board, but it's once again the same JH-7110...
...
