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Date

Disclosures

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titleRISC-V Disclosure Video
RVI_Disclosures_Female_Short.mp4

Participants

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titleMeeting Participants

Name

Affiliation

Jan Gray

Individual

Darius Rad

Bluespec

Jerry Zhao

UC Berkeley

Christian Herber

NXP

Andreas Koch

TU Darmstadt

Florian Meisel

TU Darmstadt

Mihaela Damian

TU Darmstadt

Guy Lemieux

Individual

Al Martin

Akeana

Anton Kuzmin

Individual

Christopher Dunn

Ciarian Lappin

Microchip

Cyril Koenig

ETH Zurich

David Donofrio

Tactical Computing Labs

Domingo Benitez

ULPGC

Juan

Liulu

Navaneeth Kunhi Purayil

ETH Zurich

Nick Brown

EPCC

Prasanth Mundkur

RISC-V International

Shing Wai Pun

Shinichi

Agenda and Presentations Slides

  • 7:00a: Introduction

    View file
    name2025-01-31-XLIW-Agenda.pdf

  • 7:05a: Jerry Zhao, UC Berkeley, RoCC (20 mins + 5 mins Q&A)

    View file
    name2025-01-31-XLIW-Zhao-RoCC.pdf

  • 7:30a: Christian Herber, NXP, CV-X-IF

    View file
    name2025-01-31-XLIW-Herber-CV-X-IF.pdf

  • 7:55a: Andreas Koch, TU Darmstadt, SCAIE-V

    View file
    name2025-01-31-XLIW-Koch-SCAIE-V.pdf

  • 8:20a: Jan Gray, Individual, CXU-LI

    View file
    name2025-01-31-XLIW-Gray-CXU-LI.pdf

    View file
    name2025-01-31-XLIW-Gray-CXU-LI-speaker-notes.pdf

  • 8:45a: All, Discussion and synthesis (up to 75 mins)

    View file
    name2025-01-31-XLIW-Agenda.pdf
    (again)

  • 10:00a: End

Meeting

...

Recordings / Transcripts

  • Meeting video recording website (2h35m): Zoom meeting link YouTube video.

  • Zoom meeting video : recording website (pending2h35m): Zoom meeting link.

  • Zoom meeting transcript (VTT, raw)

    View file
    nameCX TG - Extension Logic Interface Workhshop - 2025-01-31.transcript.vtt

  • Zoom meeting transcript (lightly edited)

    View file
    nameCX TG - Extension Logic Interface Workhshop - 2025-01-31.transcript

Discussion

During the “compare & contrast” open discussion segment of the meeting we considered (or tabled for later) these general aspects of the various extension logic interfaces:

  1. How much of the extension hardware & software is fixed at system and/or software build-time and how much occurs at runtime?

  2. What support for arbitrary, or fixed, custom instruction encodings? What are the implications of the interface on the ISA?

  3. Where does pipeline scheduling & hazard detection go?

  4. Value of "modular composability“? Stable CPU & CXU RTL? Does the processor core and/or the extension unit core change when combined together?

  5. What is the state model? How are multiple harts within a core handled? Can software on a thread access multiple state contexts of the same extension?

  6. What support for R or W access to hart state? (X? F? V? CSRs? Memory? Control flow? Exceptions?)

  7. Behavior of shared memory accesses by custom instructions?

  8. Support for composition of custom extensions?

  9. Simplicity vs. complexity / support for optional or "pay as you go" capabilities?

  10. What system topologies? 1 CPU :: 1 CXU, or clusters, or many :: NoC :: many?

  11. Reuse and verification ecosystem?

  12. Might you bridge one interface to another?

  13. What is the support for speculative execution? For out-of-order execution?

  14. What support for dynamically (at run-time) changeable extensions?

Notes & Action Items

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