Date
Disclosures
Participants
Agenda and Presentations Slides
7:00a: Introduction
7:05a: Jerry Zhao, UC Berkeley, RoCC (20 mins + 5 mins Q&A)
7:30a: Christian Herber, NXP, CV-X-IF
7:55a: Andreas Koch, TU Darmstadt, SCAIE-V
8:20a: Jan Gray, Individual, CXU-LI
8:45a: All, Discussion and synthesis (up to 75 mins)
(again)
10:00a: End
Meeting Recordings / Transcripts
Meeting video recording (2h35m): YouTube video.
Zoom meeting video recording website (2h35m): Zoom meeting link.
Zoom meeting transcript (VTT, raw)
Zoom meeting transcript (lightly edited)
Discussion
During the open discussion segment of the meeting we considered (or tabled for later) these general aspects of the various extension logic interfaces:
How much of the extension hardware & software is fixed at system and/or software build-time and how much occurs at runtime?
What support for arbitrary, or fixed, custom instruction encodings? What are the implications of the interface on the ISA?
Where does pipeline scheduling & hazard detection go?
Value of "modular composability“? Stable CPU & CXU RTL? Does the processor core and/or the extension unit core change when combined together?
What is the state model? How are multiple harts within a core handled? Can software on a thread access multiple state contexts of the same extension?
What support for R or W access to hart state? (X? F? V? CSRs? Memory? Control flow? Exceptions?)
Behavior of shared memory accesses by custom instructions?
Support for composition of custom extensions?
Simplicity vs. complexity / support for optional or "pay as you go" capabilities?
What system topologies? 1 CPU :: 1 CXU, or clusters, or many :: NoC :: many?
Reuse and verification ecosystem?
Might you bridge one interface to another?
What is the support for speculative execution? For out-of-order execution?
What support for dynamically (at run-time) changeable extensions?
Notes & Action Items
