Technical Steering Committee Home
About TSC
The RISC-V Technical Steering Committee (TSC) oversees the technical development of the RISC-V open-standard ISA, guiding specifications, ensuring compliance, and coordinating efforts to maintain its extensibility and open-source nature.
Members | Mailing List | Jira
TSC Chair Greg Favor | TSC Vice-Chair Philipp Tomsich |
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The TSC meets once a month on Wednesdays, from 7:00 a.m. to 9:00 a.m. Pacific Time. If you need assistance, please reach out to help@riscv.org.
RISC-V International