2025-03-05 Official Meeting Notes

Date

Mar 5, 2025

Disclosures

Participants

Voters | Quorum Required - 16

	Name	Affiliation	Voting Member	Attended

	Name	Affiliation	Voting Member	Attended
1	Allen Baum - ISA Infra HC Vice-chair	Esperanto	X	X
2	Austin (Jianlin) Gao	Tencent	X
3	Avi Timor	Google	X	X (Joined at 1:00)
4	Charlie Su	Andes	X	X (Joined at 0:32)
5	David Brash	Rivos Inc.	X	X
6	David Chen	Stream Computing	X	X
7	David Weaver	Akeana	X	X
8	Earl Killian - Unpriv IC	Aril Inc.	X	X (Joined at 0:17)
9	Erich Focht	Openchip	X
10	Frans Sijstermans	Nvidia	X	X (Left at 1:29)
11	Greg Favor - TSC Chair	Ventana Micro Systems	X	X
12	Guido Costa Souza	Brazilian Ministry of Science	X
13	Guy Lemieux - Com/Individ Elected Rep	Individual	X	X
14	Haibin Shen	Chengwei Captial	X
15	Jian Zhang	Beijing Institute of Open Source Chip	X	X
16	John Hengeveld	Intel	X
17	John Leidel - Technology HC Chair	Tactical Computing Labs	X
18	Kan Shi	ICT CAS	X
19	Ken Dockser - Strategic Elected Rep	Tenstorrent	X	X
20	Manu Gulati	Qualcomm	X	X
21	Paul Holt	Synopsys	X	X (Left at 1:00)
22	Peter Chun	Huawei	X	X (0:14 to 1:37)
23	Philipp Tomsich - TSC Vice-chair	VRULL	X	X
24	Roger Espasa - Strategic Elected Rep	Semidynamics	X
25	Shi Yijun	Sanechips/ZTE	X
26	Shubu Mukherjee	SiFive	X	X (0:17 to 0:35)
27	Siqi Zhao	Alibaba Cloud	X	X
28	Tom Zhao	Phytium	X
29	Wei Wu	ISCAS	X	x
30	Zhangzi Tan	RIOS	X

Non-Voters

Name	Affiliation	Attended

Name	Affiliation	Attended
Andrea Gallo	RISC-V	X
Andrew Dellow - Security HC Chair	Qualcomm	X
Andrew Waterman - Priv IC Vice-chair	SiFive
Anup Patel - Priv SW HC Chair	Ventana Micro Systems	X
Bill Traynor	RISC-V	X
Derek Hower	Qualcomm	X (joined at 0:44)
Greg Sterling	RISC-V	X
Jeff Scheel	RISC-V	X
Kai Liu	Alibaba	X
Krste Ansanovic	SiFive	X
Li Liu	Alibaba	X
Rafael Sene	RISC-V	X
Ravi Sahita - Security HC Vice-chair	Rivos Inc.	X
Sun Hao	Alibaba	X
Ved Shanbhogue - SOC Infra HC Chair	Rivos Inc.	X (Left 1:33)
Wang Songbo	Alibaba	X (Left 1:48)
Xinyu Qin	Alibaba	X

Agenda

Approve February 5, 2025 Meeting Minutes (link)

Questions on “discussion -- requests from AMD and Altera for SoftCPUs” (@Guy Lemieux ) - 15 minutes.

As the SoftCPU SIG Chair, I am in frequent contact with the technical leads for "soft" processor designs (ie, LUT-based rather than ASIC) used at all of the major FPGA companies. This puts me in a unique position to collect and share the needs of these RISC-V members with the TSC. (Note that all major US-based FPGA companies are RISC-V members: Altera, AMD, Efinix, Lattice, Microchip, and Bluespec supplies Achronix with processors... I'm unsure about the status of Quicklogic, or some of the newer non-US-based FPGA companies).

As a result, I have been reaching out to individuals, SIGs, and TGs about technical design objectives for RISC-V, listed below, which have been expressed from both AMD and Altera.

Most of these objectives/issues have been discussed at the SoftCPU SIG already, although some of them are newer and have not been as thoroughly discussed as others. The hope is that these issues can be addressed in 2025. I will also be reaching out to ensure that other FPGA companies are also on board (not all of them have the time capacity to attend SoftCPU SIG meetings), but I expect this will not be a problem.

I have a few reasons for sharing this list with the whole TSC:

as a committee, we should be forming a strategy for 2025 and hope this can be added to the list (among suggestions from others, which will obviously include things like >32b instructions, matrix extensions, etc)
as an individual, perhaps you can help me connect within your organization if you also have an interest in pursuing these objectives
perhaps you can point me to others outside of your organization who already have an interest or active ongoing effort to address these objectives.

Here is the list of objectives/issues:

a) CLIC needs to be ratified. What's the holdup? How can we kickstart it again? AMD is already designing their own and Altera is ironically unhappy with it not being "locked down". (I say ironically, because it's the FPGA people that are worried about finalizing a standard -- and they're the ones that are most flexible! I can only imagine how everyone else feels.) With the recent discussion in the Profiles SIG and CSC around clarifying exactly what is being certified, it seems that an interrupt controller needs to be added to a profile to create something like a "processor subsystem" that gets certified.

b) Additional support for fast interrupts via a shadow register file.

c) Reg+Reg addressing modes (rather than Reg+Imm).

d) 64b addressing mode for RV32, eg via concatenation of 2 registers. Please note that saying "RV64 solves this" is not the answer they are looking for, because a full 64b CPU datapath is too large for typical FPGA use. With a single DRAM capable of filling the entire 4GB address space, more bits are needed for other things.

e) Bitfield insertion/extraction instructions.

f) New cache management instructions to invalidate, flush and clean by cache index rather than by address.

g) Soft-processor specific profiles, which we are calling RVS. This would be a "family", like RVA, which has several variants inside. It would fit somewhere between RVB and RVM.

I know many of these things take a new TG, and some might be suitable for Fast Track. Most of the items above also have other supporters beyond soft CPUs, so the SoftCPU SIG is trying to identify the right route and partner for each of them.

I look forward to all suggestions and discussion.

Thank you,

Guy

(New) Crypto TG to Crypto SIG Proposal (Andrew Dellow, Qualcomm) - 20 min

(Closure) Microarchitecture Side Channel SIG (Andrew Dellow, Qualcomm) - 5 min

(New) Persistent Memory TG Proposal (Hao Sun, Alibaba) - 20 min

2025 Strategic Priorities (Greg) - 10 min

UnifiedDB proposal update (Andrea) - 15 min

BoD Policy Adoption Status Update (Andrea, Jeff, Rafael) - time permitting

Presentations

	Title	Presenter	File

	Title	Presenter	File
1	SoftCPU Technical Objectives 2025	Guy Lemieux
2	2025 Major Strategic Goals	Greg Favor, Philipp Tomsich, Andrea Gallo
3	UDB Updated Proposal	Andrea Gallo

Votes

Quorum Status: 17 attendees
Vote Record

Agenda Item or Motion:
Motion Made By: @Philipp Tomsich
Motion Seconded By: Paul Holt

Voting Results:

In Favor: All 18 Voting Attendees (excluding RISC-V Staff)
Opposed: None
Abstentions: None

Outcome: Motion Passed

Additional Notes: Time 0:40

Quorum Status: 17 attendees
Vote Record

Agenda Item or Motion: Close the Microarchitecture Side Channel SIG
Motion Made By: @Andrew Dellow
Motion Seconded By: @Philipp Tomsich

Voting Results:

In Favor: All 18 Voting Attendees (excluding RISC-V Staff)
Opposed: None
Abstentions: None

Outcome: Motion Passed

Additional Notes: Time: 0:55

Notes & Action Items

Attach the Persistent Memory TG proposal presentation (@Rafael Sene , @sun hao )

Review CLIC Ratification Plan and update TSC (@Rafael Sene)

Attendance report:

Summary:

SoftCPU SIG discussion
- Summary:
  Guy presents the priorities and challenges of the soft CPU Special Interest Group (SIG) for the year. The group focuses on highly parameterized processors implemented on FPGAs, which can have thousands of variants. Key issues include multi-lib support for GCC and LLVM, ratification of CLIC for interrupt control, fast interrupt handling using separate register file copies, bit field extraction and insertion, new addressing modes, and 64-bit addressing in RV32. The group also seeks to develop a soft processor profile, possibly between RVM and RVD, and a concept similar to but less extensive than a platform. Guy requests input and collaboration from other companies and SIGs to address these challenges, particularly in finding the right groups to drive some of these initiatives.
- Detailed notes:
  - Intent is to raise issues for awareness and to solicit input
  - Discussion:
    - How close is #9 to the Profile SIG discussion on-going?
      Same.
    - For #1, why is this coming to SoftCPU SIG?
      This could be raised in Toolchain SIG, but needs to be driven upstream. It seems the number of libraries that are impacted are relatively small.
    - Noted that CLIC is doing a major update.
    - Additional feedback to the TSC thread or directly to Guy.
Crypto SIG
- Summary:
  - The team also discussed the proposal to create a crypto Sig, with Andrew explaining the need for this due to the Crypto TG's completion of its work. The team agreed to proceed with the proposal.
- Detailed notes:
  - Crypto TG done, no group to drive on-going crypto discussions
  - Simplest idea is to shutdown TG and restart as SIG.
  - SiFive has agreed to help Sponsor
  - Richard and Markku will start as Acting chairs
  - Discussion:
    - Why not put this capability in Security HC?
      Specialists needed and discussion too deep for HC. We have absorbed some other SIGs into HC due to lack of participation. Crypto has a large set of experts engaged.
    - Next steps:
      - Work with the Acting Chairs to refine the PoW and send it to tech-exchange. @Rafael Sene @Andrew Dellow
Disbanding the Microarchitecture Side Channel SIG
- Summary:
  The team discussed the disbanding of the micro architecture side channel Sig, with Andrew explaining that the group's responsibilities had been absorbed into the security Hc. The team approved the disbanding of the Sig.
Persistent Memory TG Proposal
- Summary:
  - Background and overview:
    Sun presented on the concept of persistent memory, its benefits, and its timeline. He explained how memory consistency can be achieved with persistence, and discussed the potential use cases of processing memory in cloud vendors such as Microsoft and Alibaba Cloud. Sun also outlined the objectives for persistent memory, including defining the processing model, process operation, and process ordering. He mentioned that the processing model should consider the persistence model, process operation, and process ordering. Sun also discussed the importance of defining the process point and the CXL (Coherent Accelerator Processor Interface) protocol. He suggested that the task group should collaborate with software to achieve language level persistency, emphasizing the need for portability across different hardware platforms.
  - Collaborating With Software Compilers for Precision Semantics
    Sun proposed a collaboration with software compilers to support persistence semantics. He also mentioned three potential sponsors: Alibaba, a company he represents, and two other organizations discussed via email. Sun's presentation was followed by a discussion led by Jeff, where David Weaver expressed support for the proposal. Philipp raised concerns about the overlap between the proposed work and existing specifications, and the need for a clear gap analysis. Greg and Krste agreed that a gap analysis was necessary before the task group could proceed. David Brash suggested that the concept of a point of persistence might need to be introduced into the current memory model. The conversation ended with Greg affirming that defining a point of persistence was a goal of the task group's work.
  - Comprehensive Gap Analysis in Proposal
    The meeting discussed the need for a more comprehensive gap analysis in the proposal of work (POW). The team agreed that the proposal should not be limited to CXL, but should also consider other connection technologies. The discussion also touched on the need to understand usage patterns and the potential for new instructions. The team also considered the possibility of using existing instructions and device drivers, but concluded that there might be a need for more. The conversation ended with the understanding that the proposal should be adaptable to various memory technologies, including those using the TSL and the Intel Optane.
  - Refining Proposal and Involving Interested Parties
    In the meeting, Greg, Philipp, David Brash, and Krste discussed the need for a more detailed gap analysis and feedback on a proposal of work. They agreed that the proposal should be updated and refined before being presented to a broader membership review. They also discussed the possibility of involving more interested parties in the process. Andrea suggested including an early evaluation of the need for new instructions or a device driver in the updated proposal. Siqi raised a question about picking up work from previous discussions, to which Krste responded by sharing a link to a Barcelona workshop presentation.
- Detailed notes:
  - AI: attach presentation to meeting minutes.
  - Discussion
    - AI: need to clarify the technical issues which will be addressed, especially in the area of existing ISA. Also need to determine how much can be put into software (device driver).
    - Is there a concept of point of persistent in memory model?
      No.
    - Does the proposal use CXL as the only technology being investigated?
      No, but it is viewed as the most likely implementation.
    - AI: need to clarify the persistent memory technologies which should be investigated.
    - From @Krste Asanovic prior presentation on this topic:RISC-V Support for Persistent Memory Systems
  - Next steps:
    - Update and bring back to TSC for more discussion. Posting to the CCM mailing list would be a good way to continue the discussion. @Rafael Sene @sun hao
Priorities
- Summary:
  Andrea, discussed the strategic priorities for RISC-V, focusing on AI, matrix extensions on the server platform, and the security model. The Board has prioritized resolving ongoing discussions around SAIL. Ken clarified that the broader issue is having a golden model in Sail. The Board is recommending focusing on these three areas to help win adoption. The Board has identified these as the application areas where risk 5 can be a real differentiator. They also discussed increasing collaboration across the risk 5 ecosystem, improving documentation and developer experience, and extending beyond silicon vendors to understand the needs of their customers, the OEMs.
- Detailed notes:
  - BoD strategic goals discussion
    - Sail discussion is about use as Golden Model
    - Server, AI/ML, Automotive are the markets being focused on
  - Deferred Priorities to overflow
UnifiedDB follow-up
- Summary:
  - Unified DB Proposals and Integration
    Andrea proposed the adoption of Unified DB by various technical and task groups, with the aim of integrating its components into existing workflows. He suggested that Unified DB's assets, such as the machine-readable format and the Assembly Reference manual, could be beneficial to various groups. Andrea also proposed the formation of a Unified DB SIG to oversee the evolution of these assets and ensure their continued compatibility.
  - Unified DB Sig Proposal Refinement
    In the meeting, the discussion was focused on refining a proposal for a Unified DB SIG. Andrea summarized the main points, and the team agreed that the proposal was a good resolution to previous concerns about disruption. They decided to update the overall proposal and submit it to the TSC via email for broader comment. There was also a suggestion to have an overflow meeting next week to discuss persistent memory and strategic priorities. The team agreed to work asynchronously on these items, with the aim of having an updated proposal by next week. It was also clarified that all group proposals now require TSC approval.
- Detailed notes:
  - Unified DB SIG would engage with various groups and work on integration of UDB per slide #2
  - Keep UDB as SIG and integration point
  - Discussion:
    - Many groups looking at UDB are under ISA Infra HC.
    - Organization appears to make sense and we don’t.
  - Next steps:
    - Update proposal with details from Andrea’s work and submit to CCM mailing list. @Rafael Sene @Derek Hower
Overflow meeting for next week likely. Decision will be made on Monday, March 10.

Adjournment

Motion to Adjourn Made By: @Philipp Tomsich
Seconded By: @Allen Baum
Time Adjourned: 2:04

Technical Steering Committee