Info
This document outlines the plan to ratify a RISC-V Specification, establishing a solid foundation and clear expectations for the entire specification development lifecycle. The timeline set here will serve as a reference to monitor progress and ensure milestones are met. Investing in a well-prepared plan promotes effective communication, enhances collaboration, and streamlines the process.

About

Background

Select one of the options below (ISA or NON-ISA) and complete the table with the required information.

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title	ISA

Item	Description	Plan	Resources
Opcode	Enough opcode encoding to support GCC.	Implemented in LLVM	Codasip+Cambridge Uni
Simulator	Enough simulator support so that basic RISC-V tests can be run. See the policy for more details.	QEMU and Sail support implemented	Codasip+Cambridge Uni
psABI	ABI extensions (if necessary)	Planned	Jessica Clarke + Alex Richardson
GCC	Support on GCC (optimizations not required)	N/A, LLVM instead
LLVM	Support on LLVM (optimizations not required)	Full support implemented in fork	Codasip+Cambridge Uni
RISC-V Test Input	Test configuration input (YAML schema & values, Test Coverage YAML rules, see the policy)
RISC-V Tests	Basic tests that do not cover corner cases. See the policy for more details.	Available on demand	Codasip
RISC-V SAIL	Enablement of the new specification/extension as part of the RISC-V SAIL Golden Model.	Implemented	Codasip

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title	NON-ISA

Item	Description	Plan	Resources
Code	Describe any updated software project by name and, if possible, by version. make each project its own row.
Tests	Describe testing to validate specification compatibility if applicable. This may be ACT, PCT, or other tests. Make each test project its own row.

Info
To define you plan milestone dates, please use the https://tech.riscv.org/plan/.

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