This page contains the list of all archived ratified technical specification version. For the most recent versions of any specification, see the RISC-V Technical Specifications page.
NOTE: specifications not found on this page have only one version and thus are only available on the RISC-V Technical Specifications page.
Archive Contents
ISA Specifications
These sections contain previous, complete versions of the two ISA specification volumes.
The RISC-V Instruction Set Manual Volume I: Unprivileged ISA
The RISC-V Instruction Set Manual Volume II: Privileged Architecture
ISA Ratification Specifications
This section contains the specifications which were independently ratified and subsequently have been pulled into the appropriate ISA volumes published on the RISC-V Technical Specifications page.
Specification name | Ratified | New extension(s) or Profile(s) | RISC-V Community |
---|
RISC-V Supervisor Counter Delegation | March 2024 | Smcdeleg, Ssccfg | Privileged Horizontal Committee |
May-Be-Operations | March 2024 | Zimop, Zcmop | Unprivileged Horizontal Committee |
RISC-V Indirect CSR Access (Smcsrind/Sscsrind) | February 2024 | Smcsrind, Sscsrind | Privileged Horizontal Committee |
RISC-V Integer Conditional (Zicond) operations extension | November 2023 | Zicond | Unprivileged Horizontal Committee |
Hardware Updating of PTE A/D Bits (Svadu) | November 2023 | Svadu | Privileged Horizontal Committee |
RISC-V Cycle and Instret Privilege Mode Filtering (Smcntrpmf) | November 2023 | Smcntrpmf | Privileged Horizontal Committee |
Atomic Compare-and-Swap (CAS) Instructions (Zacas) | November 2023 | Zacas | Unprivileged Horizontal Committee |
RISC-V Cryptography Extensions Volume II: Vector Instructions | September 2023 | Zvbb, Zvbc, Zvkb, Zvkg, Zvkn, Zvknc, Zvkned, Zvkng, Zvknha, Zvknhb, Zvks, Zvksc, Zvksed, Zvksg, Zvksh, Zvkt | Unprivileged Horizontal Committee |
"Zfa" Standard Extension for Additional Floating-Point Instructions | September 2023 | Zfa | Unprivileged Horizontal Committee |
RISC-V Advanced Interrupt Architecture | June 2023 | Smaia, Ssaia | Privileged Horizontal Committee |
“Zvfh/Zvfhmin:” Vector Extension for Half-Precision Floating-Point Arithmetic/Vector Extension for Minimal Half- Precision Floating-Point Arithmetic | June 2023 | Zvfh, Zvfhmin | Unprivileged Horizontal Committee |
“Zihintntl” Non-Temporal Locality Hints | May 2023 | Zihintntl | Unprivileged Horizontal Committee |
RISC-V Code Size Reduction | April 2023 | Zca, Zcb, Zcd, Zce, Zcf, Zcmp, Zcmt | Unprivileged Horizontal Committee |
"Zicntr" and "Zihpm" Counters | March 2023 | Zicntr, Zihpm | Unprivileged Horizontal Committee |
RV32E and RV64E Base Integer Instruction Sets | January 2023 | RV32E/RV64E | Unprivileged Horizontal Committee |
“Ztso” Standard Extension for Total Store Ordering | January 2023 | Ztso | Unprivileged Horizontal Committee |
RISC-V Wait-on-Reservation-Set (Zawrs) extension | November 2022 | Zawrs | Unprivileged Horizontal Committee |
Zmmul Extension | June 2022 | Zmmul | Unprivileged Horizontal Committee |
PMP Enhancements for memory access and execution prevention on Machine mode (Smepmp) | November 2021 | Smepmp | Privileged Horizontal Committee |
RISC-V Privileged Architecture 1.12 | November 2021 | Sm1p12, Ss1p12, Sv57, Hypervisor, Svinval, Svnapot, Svpbmt | Privileged Horizontal Committee |
RISC-V Base Cache Management Operation ISA Extensions | November 2021 | Zicbom, Zicbop, Zicboz | Unprivileged Horizontal Committee |
RISC-V Bit-Manipulation ISA-extensions | November 2021 | Zba, Zbb, Zbc, Zbs | Unprivileged Horizontal Committee |
RISC-V Count Overflow and Mode-Based Filtering Extension | November 2021 | Sscofpmf | Privileged Horizontal Committee |
RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions | November 2021 | Zbkb, Zbkc, Zbkx, Zknd, Zkne, Zknh, Zksed, Zksh, Zkn, Zks, Zkt, Zk, Zkr | Unprivileged Horizontal Committee |
RISC-V State Enable Extension | November 2021 | Smstateen | Privileged Horizontal Committee |
RISC-V "stimecmp / vstimecmp" Extension | November 2021 | Sstc | Privileged Horizontal Committee |
RISC-V Vector Extension | November 2021 | Zve32x, Zve32f, Zve64x, Zve64f, Zve64d, Zve, Zvl32b, Zvl64b, Zvl128b, Zvl256b, Zvl512b, Zvl1024b, Zvl, Zv | Unprivileged Horizontal Committee |
"Zfh" and "Zfhmin" Standard Extensions for Half-Precision Floating-Point | November 2021 | Zfh, Zfhmin | Unprivileged Horizontal Committee |
"Zfinx", "Zdinx", "Zhinx", "Zhinxmin": Standard Extensions for Floating-Point in Integer Registers | November 2021 | Zfinx, Zdinx, Zhinx, Zhinxmin | Unprivileged Horizontal Committee |
“Zihintpause” Pause Hint | February 2021 | Zihintpause | Unprivileged Horizontal Committee |
Non-ISA Specifications
These sections contain previous versions of non-ISA specifications.
NOTE: specifications not found on this page have only one version and thus are only available on the RISC-V Technical Specifications page.
RISC-V Supervisor Binary Interface Specification
Version | Publish Date | Description | RISC-V Community | Source Repository |
---|
1.0.0 | May 2022 | Describes the RISC-V Supervisor Binary Interface, known from here on as SBI which enables supervisor-mode (S-mode or VS-mode) software to be portable across all RISC-V implementations by defining an abstraction for platform (or hypervisor) specific functionality. | Privileged Software Horizontal Committee | riscv-non-isa/riscv-sbi-doc |