As the SoftCPU SIG Chair, I am in frequent contact with the technical leads for "soft" processor designs (ie, LUT-based rather than ASIC) used at all of the major FPGA companies. This puts me in a unique position to collect and share the needs of these RISC-V members with the TSC. (Note that all major US-based FPGA companies are RISC-V members: Altera, AMD, Efinix, Lattice, Microchip, and Bluespec supplies Achronix with processors... I'm unsure about the status of Quicklogic, or some of the newer non-US-based FPGA companies).
As a result, I have been reaching out to individuals, SIGs, and TGs about technical design objectives for RISC-V, listed below, which have been expressed from both AMD and Altera.
Most of these objectives/issues have been discussed at the SoftCPU SIG already, although some of them are newer and have not been as thoroughly discussed as others. The hope is that these issues can be addressed in 2025. I will also be reaching out to ensure that other FPGA companies are also on board (not all of them have the time capacity to attend SoftCPU SIG meetings), but I expect this will not be a problem.
I have a few reasons for sharing this list with the whole TSC:
as a committee, we should be forming a strategy for 2025 and hope this can be added to the list (among suggestions from others, which will obviously include things like >32b instructions, matrix extensions, etc)
as an individual, perhaps you can help me connect within your organization if you also have an interest in pursuing these objectives
perhaps you can point me to others outside of your organization who already have an interest or active ongoing effort to address these objectives.
Here is the list of objectives/issues:
a) CLIC needs to be ratified. What's the holdup? How can we kickstart it again? AMD is already designing their own and Altera is ironically unhappy with it not being "locked down". (I say ironically, because it's the FPGA people that are worried about finalizing a standard -- and they're the ones that are most flexible! I can only imagine how everyone else feels.) With the recent discussion in the Profiles SIG and CSC around clarifying exactly what is being certified, it seems that an interrupt controller needs to be added to a profile to create something like a "processor subsystem" that gets certified.
b) Additional support for fast interrupts via a shadow register file.
c) Reg+Reg addressing modes (rather than Reg+Imm).
d) 64b addressing mode for RV32, eg via concatenation of 2 registers. Please note that saying "RV64 solves this" is not the answer they are looking for, because a full 64b CPU datapath is too large for typical FPGA use. With a single DRAM capable of filling the entire 4GB address space, more bits are needed for other things.
e) Bitfield insertion/extraction instructions.
f) New cache management instructions to invalidate, flush and clean by cache index rather than by address.
g) Soft-processor specific profiles, which we are calling RVS. This would be a "family", like RVA, which has several variants inside. It would fit somewhere between RVB and RVM.
I know many of these things take a new TG, and some might be suitable for Fast Track. Most of the items above also have other supporters beyond soft CPUs, so the SoftCPU SIG is trying to identify the right route and partner for each of them.
I look forward to all suggestions and discussion.
Thank you,
Guy
