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This document outlines the plan to ratify a RISC-V Specification, establishing a solid foundation and clear expectations for the entire specification development lifecycle. The timeline set here will serve as a reference to monitor progress and ensure milestones are met. Investing in a well-prepared plan promotes effective communication, enhances collaboration, and streamlines the process.

About

  • Specification Name:

  • Task Group:

  • Task Group Charter:

  • Spec Jira:

Background

Overview

Stakeholders Identification

References: Active Groups and Specifications Under Development

Design Considerations

Proof-of-Concept and Tests

Software Ecosystem Impacts

Freeze Checklists

Select one of the options below (ISA or NON-ISA) and complete the table with the required information.

 ISA

Item

Description

Plan

Resources

Opcode

Enough opcode encoding to support GCC.

Simulator

Enough simulator support so that basic RISC-V tests can be run. See the policy for more details.

psABI

ABI extensions (if necessary)

GCC

Support on GCC (optimizations not required)

LLVM

Support on LLVM (optimizations not required)

RISC-V Test Input

Test configuration input (YAML schema & values, Test Coverage YAML rules, see the policy)

RISC-V Tests

Basic tests that do not cover corner cases. See the policy for more details.

RISC-V SAIL

Enablement of the new specification/extension as part of the RISC-V SAIL Golden Model.

 NON-ISA

Item

Description

Plan

Resources

Code

Describe any updated software project by name and, if possible, by version. make each project its own row.

Tests

Describe testing to validate specification compatibility if applicable. This may be ACT, PCT, or other tests. Make each test project its own row.

Key Milestones

To define you plan milestone dates, please use the https://tech.riscv.org/plan/.

Milestone

Date

Plan Approval

Internal Review Start

ARC Review Freeze Request

Freeze

Public Review Start

TSC Ratification Approval

BoD Ratification Approval

Additional Notes


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