Note
This document is currently a draft.

Info
This document outlines the plan to ratify a RISC-V Specification, establishing a solid foundation and clear expectations for the entire specification development lifecycle. The timeline set here will serve as a reference to monitor progress and ensure milestones are met. Investing in a well-prepared plan promotes effective communication, enhances collaboration, and streamlines the process.

About

Specification Name: Composable Custom Extensions
Task Group: Composable Custom Extensions Task Group
Task Group Charter: Charter
Spec Jira:
Jira Legacy
server System Jira
serverId 4d3dce95-b4be-35da-b49f-ec8432d8f473
key RVS-2611

Background

Reuse of multiple custom extensions is rare, in part because custom extensions may conflict in use of custom instructions and CSRs, and because there is no common programming model or API for custom extensions. This can lead to disjoint solution silos and ecosystem fragmentation. To help address this gap, the TG will advance interop standards that make it easier to reuse certain kinds of custom extensions, enabling a plug-and-play ecosystem of such extensions.

Overview

The TG will define a framework of ISA and non-ISA specifications that together facilitate the decentralized, cooperative reuse of the custom instruction and custom CSR space, enabling practical reuse, within a system, of multiple, independently authored composable custom extensions (CXs), CX libraries, and CX unit (CXU) logic modules, while also remaining backwards compatible with legacy custom extensions.

Stakeholders Identification

Privileged Architecture HC - ISA changes
SoftCPU SIG - Use case
Unified Discovery TG - Discovery
Platform Runtime Services TG - Discovery, configuration
Toolchains SIG - ABI support
psABI - ABI

References: Active Groups and Specifications Under Development

Design Considerations

Specifications are being designed to be useful to a variety of design point: FPGA and ASIC, microcontroller through HPC.
Proof of concept will demonstrate supervisor operating system, but specifications are intended to be useful for M and M/U only systems as well.

Proof-of-Concept and Tests

Proof-of Concept

Reference designs for all components that are specified, demonstrating interoperation where deemed necessary; an implementation of the API and ABI as part of implementing an end-to-end software PoC, including all discovery and configuration components.

...

Tests (ACT for ISA or Software)

Planned

Software Ecosystem Impacts

Operating systems

Linux - Discovery and configuration, context management, access control

...

Applications (direct use)

Not planned

Freeze Checklists

Select one of the options below (ISA or NON-ISA) and complete the table with the required information.

Expand

title	ISA

Item	Description	Plan
Opcode	Enough opcode encoding to support GCC.	Planned, expect 1-3 opcodes and ~10 CSRs
Simulator	Enough simulator support so that basic RISC-V tests can be run. See the policy for more details.	QEMU & SAIL Planned
psABI	ABI extensions (if necessary)	Planned, CX specific ABI
GCC	Support on GCC (optimizations not required)	Planned
LLVM	Support on LLVM (optimizations not required)	Not Planned
RISC-V Test Input	Test configuration input (YAML schema & values, Test Coverage YAML rules, see the policy)	Planned
RISC-V Tests	Basic tests that do not cover corner cases. See the policy for more details.	Planned
RISC-V SAIL	Enablement of the new specification/extension as part of the RISC-V SAIL Golden Model.	Planned