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This document outlines the plan to ratify a RISC-V Specification, establishing a solid foundation and clear expectations for the entire specification development lifecycle. The timeline set here will serve as a reference to monitor progress and ensure milestones are met. Investing in a well-prepared plan promotes effective communication, enhances collaboration, and streamlines the process.

About

Background

The goal of the CHERI TG is to define a capability-based security extension.

CHERI provides deterministic spatial and temporal memory safety, and low-cost scalable compartmentalization features and is a fundamental step forward in terms of security for the RISC-V ecosystem.

Building on over a decade of pioneering research by the University of Cambridge and SRI International, the CHERI technology has been implemented by Arm on the Morello 7nm SoC evaluation platform, and many processors have been developed by academia and the industry (Microsoft, Google, Codasip, lowRISC…)

Overview

Stakeholders Identification

References: Active Groups and Specifications Under Development

We will work closely with the following groups to ensure the extension meets all requirements:

  • Security HC as well as Priv+Unpriv IC

  • CHERI SIG

  • psABI (to define the new pure-capability ABI)

  • Architectural Testing (to define a testsuite for CHERI-RISC-V)

  • Formal modelling (to upstream a CHERI-RISC-V Sail model)

  • Apps and Tools Software HC

  • SBI Specification

Design Considerations

The CHERI extension has been designed to be fully binary compatible with existing RISC-V code.

Proof-of-Concept and Tests

Software Ecosystem Impacts

Freeze Checklists

Select one of the options below (ISA or NON-ISA) and complete the table with the required information.

 ISA

Item

Description

Plan

Resources

Opcode

Enough opcode encoding to support GCC.

Full support in LLVM: https://github.com/CHERI-Alliance/llvm-project

Codasip+Cambridge Uni

Simulator

Enough simulator support so that basic RISC-V tests can be run. See the policy for more details.

QEMU support implemented: https://github.com/CHERI-Alliance/qemu

Codasip+Cambridge Uni

psABI

ABI extensions (if necessary)

Planned

Jessica Clarke + Alex Richardson

GCC

Support on GCC (optimizations not required)

N/A, using LLVM instead

LLVM

Support on LLVM (optimizations not required)

Full support: https://github.com/CHERI-Alliance/llvm-project

Codasip+Cambridge Uni

RISC-V Test Input

Test configuration input (YAML schema & values, Test Coverage YAML rules, see the policy)

RISC-V Tests

Basic tests that do not cover corner cases. See the policy for more details.

Available on demand

Codasip

RISC-V SAIL

Enablement of the new specification/extension as part of the RISC-V SAIL Golden Model.

Implemented: https://github.com/CHERI-Alliance/sail-cheri-riscv

Codasip

 NON-ISA

Item

Description

Plan

Resources

Code

Describe any updated software project by name and, if possible, by version. make each project its own row.

Tests

Describe testing to validate specification compatibility if applicable. This may be ACT, PCT, or other tests. Make each test project its own row.

Key Milestones

To define you plan milestone dates, please use the https://tech.riscv.org/plan/.

Milestone

Date

Plan Approval

Internal Review Start

ARC Review Freeze Request

Freeze

Public Review Start

TSC Ratification Approval

BoD Ratification Approval

Additional Notes

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  • No labels

RISC-V International