This page contains the list of all archived ratified technical specification version. For the most recent versions of any specification, see the RISC-V Technical Specifications page.

NOTE: specifications not found on this page have only one version and thus are only available on the RISC-V Technical Specifications page.

Archive Contents

1 ISA Specifications
- 1.1 The RISC-V Instruction Set Manual Volume I: Unprivileged ISA
- 1.2 The RISC-V Instruction Set Manual Volume II: Privileged Architecture
2 ISA Ratification Specifications
3 Non-ISA Specifications
- 3.1 RISC-V External Debug Specification
- 3.2 RISC-V Supervisor Binary Interface Specification

ISA Specifications

These sections contain previous, complete versions of the two ISA specification volumes.

The RISC-V Instruction Set Manual Volume I: Unprivileged ISA

Version	Publish Date	RISC-V Community	Source Repository

Version	Publish Date	RISC-V Community	Source Repository
20191213	Dec. 2019	Unprivileged Horizontal Committee	riscv/riscv-isa-manual

The RISC-V Instruction Set Manual Volume II: Privileged Architecture

Version	Publish Date	RISC-V Community	Source Repository

Version	Publish Date	RISC-V Community	Source Repository
20211203	Dec. 2021	Privileged Horizontal Committee	riscv/riscv-isa-manual

ISA Ratification Specifications

This section contains the specifications which were independently ratified and subsequently have been pulled into the appropriate ISA volumes published on the RISC-V Technical Specifications page.

Specification name	Ratified	New extension(s) or Profile(s)	RISC-V Community	Source

Specification name	Ratified	New extension(s) or Profile(s)	RISC-V Community	Source
RISC-V Supervisor Counter Delegation	March 2024	Smcdeleg, Ssccfg	Privileged Horizontal Committee	riscv-smcdeleg-ssccfg
May-Be-Operations	March 2024	Zimop, Zcmop	Unprivileged Horizontal Committee
RISC-V Indirect CSR Access (Smcsrind/Sscsrind)	February 2024	Smcsrind, Sscsrind	Privileged Horizontal Committee	riscv-indirect-csr-access
RISC-V Integer Conditional (Zicond) operations extension	November 2023	Zicond	Unprivileged Horizontal Committee	riscv-zicond
Hardware Updating of PTE A/D Bits (Svadu)	November 2023	Svadu	Privileged Horizontal Committee	riscv-svadu
RISC-V Cycle and Instret Privilege Mode Filtering (Smcntrpmf)	November 2023	Smcntrpmf	Privileged Horizontal Committee	riscv-smcntrpmf
Atomic Compare-and-Swap (CAS) Instructions (Zacas)	November 2023	Zacas	Unprivileged Horizontal Committee	riscv-zacas
RISC-V Cryptography Extensions Volume II: Vector Instructions	September 2023	Zvbb, Zvbc, Zvkb, Zvkg, Zvkn, Zvknc, Zvkned, Zvkng, Zvknha, Zvknhb, Zvks, Zvksc, Zvksed, Zvksg, Zvksh, Zvkt	Unprivileged Horizontal Committee	riscv-crypto
"Zfa" Standard Extension for Additional Floating-Point Instructions	September 2023	Zfa	Unprivileged Horizontal Committee
RISC-V Advanced Interrupt Architecture	June 2023	Smaia, Ssaia	Privileged Horizontal Committee	riscv-aia
“Zvfh/Zvfhmin:” Vector Extension for Half-Precision Floating-Point Arithmetic/Vector Extension for Minimal Half- Precision Floating-Point Arithmetic	June 2023	Zvfh, Zvfhmin	Unprivileged Horizontal Committee
“Zihintntl” Non-Temporal Locality Hints	May 2023	Zihintntl	Unprivileged Horizontal Committee
RISC-V Code Size Reduction	April 2023	Zca, Zcb, Zcd, Zce, Zcf, Zcmp, Zcmt	Unprivileged Horizontal Committee	riscv-code-size-reduction
"Zicntr" and "Zihpm" Counters	March 2023	Zicntr, Zihpm	Unprivileged Horizontal Committee
RV32E and RV64E Base Integer Instruction Sets	January 2023	RV32E/RV64E	Unprivileged Horizontal Committee
“Ztso” Standard Extension for Total Store Ordering	January 2023	Ztso	Unprivileged Horizontal Committee
RISC-V Wait-on-Reservation-Set (Zawrs) extension	November 2022	Zawrs	Unprivileged Horizontal Committee	riscv-zawrs
Zmmul Extension	June 2022	Zmmul	Unprivileged Horizontal Committee
PMP Enhancements for memory access and execution prevention on Machine mode (Smepmp)	November 2021	Smepmp	Privileged Horizontal Committee
RISC-V Privileged Architecture 1.12	November 2021	Sm1p12, Ss1p12, Sv57, Hypervisor, Svinval, Svnapot, Svpbmt	Privileged Horizontal Committee
RISC-V Base Cache Management Operation ISA Extensions	November 2021	Zicbom, Zicbop, Zicboz	Unprivileged Horizontal Committee
RISC-V Bit-Manipulation ISA-extensions	November 2021	Zba, Zbb, Zbc, Zbs	Unprivileged Horizontal Committee	riscv-bitmanip
RISC-V Count Overflow and Mode-Based Filtering Extension	November 2021	Sscofpmf	Privileged Horizontal Committee	riscv-count-overflow
RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions	November 2021	Zbkb, Zbkc, Zbkx, Zknd, Zkne, Zknh, Zksed, Zksh, Zkn, Zks, Zkt, Zk, Zkr	Unprivileged Horizontal Committee	riscv-crypto
RISC-V State Enable Extension	November 2021	Smstateen	Privileged Horizontal Committee	riscv-state-enable
RISC-V "stimecmp / vstimecmp" Extension	November 2021	Sstc	Privileged Horizontal Committee	riscv-time-compare
RISC-V Vector Extension	November 2021	Zve32x, Zve32f, Zve64x, Zve64f, Zve64d, Zve, Zvl32b, Zvl64b, Zvl128b, Zvl256b, Zvl512b, Zvl1024b, Zvl, Zv	Unprivileged Horizontal Committee	riscv-v-spec
"Zfh" and "Zfhmin" Standard Extensions for Half-Precision Floating-Point	November 2021	Zfh, Zfhmin	Unprivileged Horizontal Committee
"Zfinx", "Zdinx", "Zhinx", "Zhinxmin": Standard Extensions for Floating-Point in Integer Registers	November 2021	Zfinx, Zdinx, Zhinx, Zhinxmin	Unprivileged Horizontal Committee	riscv-zfinx
“Zihintpause” Pause Hint	February 2021	Zihintpause	Unprivileged Horizontal Committee

Non-ISA Specifications

These sections contain previous versions of non-ISA specifications.

NOTE: specifications not found on this page have only one version and thus are only available on the RISC-V Technical Specifications page.

RISC-V External Debug Specification

Version	Published	Description	RISC-V Community	Source

Version	Published	Description	RISC-V Community	Source
0.13.2	May 2019	Outlines a standard architecture for external debug support on RISC-V platforms.	SOC Infrastructure Horizontal Committee	riscv/tech-debug-spec

RISC-V Supervisor Binary Interface Specification

Version	Published	Description	RISC-V Community	Source

Version	Published	Description	RISC-V Community	Source
1.0.0	May 2022	Describes the RISC-V Supervisor Binary Interface, known from here on as SBI which enables supervisor-mode (S-mode or VS-mode) software to be portable across all RISC-V implementations by defining an abstraction for platform (or hypervisor) specific functionality.	Privileged Software Horizontal Committee	riscv-non-isa/riscv-sbi-doc

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RISC-V Technical Specifications Archive