This document outlines the plan to ratify a RISC-V Specification, establishing a solid foundation and clear expectations for the entire specification development lifecycle. The timeline set here will serve as a reference to monitor progress and ensure milestones are met. Investing in a well-prepared plan promotes effective communication, enhances collaboration, and streamlines the process.

About

Specification Name: Hart Trace Interface
Task Group: HTI Fast-track
Task Group Charter: Extract chapter 4 from the Enhanced Trace for RISC-V standard into a separate standalone specification. No normative changes will be made to the text.
Spec Jira: https://lf-riscv.atlassian.net/browse/RVS-3561

Background

The Efficient Trace for RISC-V standard (E-Trace) includes the definition of an interface for communicating information between a hart and a Trace Encoder external to the hart. However, there is nothing in this interface that is specific to E-Trace, and indeed there are references to this chapter in the N-Trace spec, and it is equally applicable to any other future trace encoding solutions.

Overview

Stakeholders Identification

DTPM SIG

References: Active Groups and Specifications Under Development

Design Considerations

N/A

Proof-of-Concept and Tests

N/A

Software Ecosystem Impacts

N/A

Freeze Checklists

Select one of the options below (ISA or NON-ISA) and complete the table with the required information.

Item	Description	Plan	Resources

Item	Description	Plan	Resources
Opcode	Enough opcode encoding to support GCC.
Simulator	Enough simulator support so that basic RISC-V tests can be run. See the policy for more details.
psABI	ABI extensions (if necessary)
GCC	Support on GCC (optimizations not required)
LLVM	Support on LLVM (optimizations not required)
RISC-V Test Input	Test configuration input (YAML schema & values, Test Coverage YAML rules, see the policy)
RISC-V Tests	Basic tests that do not cover corner cases. See the policy for more details.
RISC-V SAIL	Enablement of the new specification/extension as part of the RISC-V SAIL Golden Model.

Item	Description	Plan	Resources

Item	Description	Plan	Resources
Code	Describe any updated software project by name and, if possible, by version. make each project its own row.
Tests	Describe testing to validate specification compatibility if applicable. This may be ACT, PCT, or other tests. Make each test project its own row.

I don’t believe any of the non ISA freeze checklist options are appropriate here as there are no normative changes.

Key Milestones

To define you plan milestone dates, please use the RISC-V Spec Plan Editor.

Milestone	Date

Milestone	Date
Plan Approval	Apr 17, 2025
Internal Review Start	Jun 3, 2025
ARC Review Freeze Request	Jul 31, 2025
Freeze	Sep 24, 2025
Public Review Start	Sep 25, 2025
TSC Ratification Approval	Nov 14, 2025
BoD Ratification Approval	Nov 27, 2025

SOC Infrastructure

Hart Trace Interface Fast Track