ARC Minutes 2025-03-11

Minutes

Content:

• The ARC is providing guidance to the Debug TG about a "bug fix" to Debug 1.0 regarding the use of current versus effective privilege mode by load/store instructions where the instructions use effective privilege mode but debug triggers use current privilege mode (namely the hypervisor loads/stores and loads/stores under MPRV=1).

  • The ARC recommends that this "fix" be pursued as a new fast-track arch extension - tentatively named Sdtrigepm - that is distinct from modifying the existing Sdtrig 1.0 ISA extension that is part of Debug 1.0.
    
    

• Review of the RPMI extension is nearing completion.  Since last week most of the outstanding issues have been fixed by the TG and only one issue remains outstanding (and is being worked on by the TG).
  
  

• In response to a question about the handling of reserved FENCE encodings, there will be clarifications made to the spec regarding the following points:

  • The FENCE section describes a number of fence instructions (with predecessor/successor options) that are distinguished by the fm field.  These are not intended or constrained to simply all be minor variants of each other.   The FENCE, FENCE.TSO, and reserved encodings with other fm values represent eight different classes of fence instructions.

  • The statement that reserved encodings should be implemented as FENCE instructions with fm=0 also includes the rs1/rd fields as all zeroes (with the p*/s* fields remaining the same as in the original instruction).

  • Some other aspects of the handling of reserved encodings.
    
    

• Review of the Supervisor Domains spec has started, with some initial feedback regarding the following items to be provided to the TG:

  • Extending AIA interrupt handling for multiple supervisor domains.

  • The current lack of extending the APLIC to support multiple supervisor domains (and how that can be done).

  • When the stimecmp CSR is context switched between supervisor domains, the issue of enabling hardware to recognize when a timer expires for a switched out domain needs to be considered - which may result in adding support for a "fast access" form of mtimecmp.
    
    

• Review of the CHERI spec has started

  • The first set of feedback centers around the need for the spec to be better structured and architecturally layered by privilege mode (similar to the current unpriv/priv architecture).

  • There should be a clear base CHERI ISA with all standard RISC-V arch extensions defined to layer by default on top unless otherwise stated, and for CHERI sections to be added to the chapters for arch extensions that are affected or modified by CHERI.

    • The ARC suggests RV64CH and RV32CH as the names of the CHERI base ISAs (on top of which existing RISC-V extensions and other CHERI extensions layer on top).

  • Similar to the Priv architecture, there should be separate CHERI specs per privilege level.

  • The virtual memory chapter seems tied to one prototype scheme versus describing the deltas and additions wrt the existing Sv* translation modes.

  • The compatibility mode should be clearly described as an option to the base CHERI ISA.

  • There are some questions about the large number of options and seeming experimental features.

  • Options should be explicitly named.  (This is a WIP for the current priv arch as well.)