About

Specification Name: PTE Reserved-for-Software Bits 60-59
Task Group: Fast-Track
Task Group Charter: N/A
Spec Jira: https://lf-riscv.atlassian.net/browse/RVS-3647

Background

Operating systems, such as FreeBSD [1], Linux [2], and Windows [3], frequently use reserved bits within Page Table Entries (PTEs) to store metadata for advanced memory management features, such as page access tracking, and software-managed dirty bits. Embedding these metadata bits directly within the PTEs allows for fast access with minimal overhead, avoiding costly lookup in auxiliary data structures.

Currently, RISC-V reserves two bits in PTEs for software use. However, modern operating systems like Linux require at least three metadata bits to fully support key features and a feature needing a fourth bit appears to be on the horizon.

This limitation forces kernel developers to make a compile-time trade off, selecting only two out of three
possible functionalities [4]. For further details see this this thread on the Linux kernel mail list.

We propose a fast-track extension called Svrsw60t59b to address this limitation.

Overview

The Svrsw60t59b extension addresses this by introducing two additional software-reserved bits, increasing the total from two to four. This not only resolves the immediate constraint, enabling full support for existing use cases, but also provides an extra bit for future expansion, ensuring compatibility with evolving operating system requirements.

A companion IOMMU non-ISA extension is added to enumerate the support of Svrsw60t59b in the IOMMU using a capability register bit.

Stakeholders Identification

Privileged IC
IOMMU TG
SoC Infra. HC
Priv. SW HC
Virtualization SIG

References: Active Groups and Specifications Under Development

Design Considerations

The Svrsw60t59b extension addresses the limitation of RSW bits in PTEs by introducing two additional software-reserved bits, increasing the total from two to four. This not only resolves the immediate constraint, enabling full support for existing use cases, but also provides an extra bit for future expansion, ensuring compatibility with evolving operating system requirements.

Proof-of-Concept and Tests

The QEMU ISA emulator will be extended to support Svrsw60t59b
Linux kernel extended to use the additional reserved for software bits to simultaneously enable the following Linux kernel features that depend on these bits:
- devmap
- soft-dirty
- uffd-wp

Software Ecosystem Impacts

Benefits the Linux kernel by allow enabling of the following features simultaneously in the kernel:

devmap
soft-dirty
uffd-wp

This enables usages such as VM live-migration and checkpoint creation/restore (CRIU) to be supported by the RISC-V Linux kernel.

Freeze Checklists

Select one of the options below (ISA or NON-ISA) and complete the table with the required information.

Item	Description	Plan	Resources

Item	Description	Plan	Resources
Opcode	Enough opcode encoding to support GCC.	N/A - no new opcodes required
Simulator	Enough simulator support so that basic RISC-V tests can be run. See the policy for more details.	Planned - QEMU (https://lists.gnu.org/archive/html/qemu-riscv/2025-03/msg00218.html ) Planned - Spike (https://github.com/riscv-software-src/riscv-isa-sim/pull/1936 )	Rivos Inc.
psABI	ABI extensions (if necessary)	N/A - not impacted.
GCC	Support on GCC (optimizations not required)	N/A - not impacted.
LLVM	Support on LLVM (optimizations not required)	N/A - not impacted.
RISC-V Test Input	Test configuration input (YAML schema & values, Test Coverage YAML rules, see the policy)	Planned - riscv-config (https://github.com/riscv-software-src/riscv-config/pull/195 )	Rivos Inc.
RISC-V Tests	Basic tests that do not cover corner cases. See the policy for more details.	Planned (https://github.com/riscv-non-isa/riscv-arch-test/pull/621 )	Rivos Inc.
RISC-V SAIL	Enablement of the new specification/extension as part of the RISC-V SAIL Golden Model.	Planned (https://github.com/riscv/sail-riscv/pull/797 )	Rivos Inc.

Item	Description	Plan	Resources

Item	Description	Plan	Resources
Code	Describe any updated software project by name and, if possible, by version. make each project its own row.	Planned - QEMU - to add the capability bit.	Rivos Inc.
Tests	Describe testing to validate specification compatibility if applicable. This may be ACT, PCT, or other tests. Make each test project its own row.	Planned - extend IOMMU C mode implementation and sample tests with additional capability bit.	Rivos Inc.

Key Milestones

To define you plan milestone dates, please use the https://tech.riscv.org/plan/.

Milestone	Date

Milestone	Date
Plan Approval	May 20, 2025
Internal Review Start	Aug 30, 2025
ARC Review Freeze Request	Nov 13, 2025
Freeze	Dec 6, 2025
Public Review Start	Dec 20, 2025
TSC Ratification Approval	Feb 4, 2026
BoD Ratification Approval	Feb 18, 2026