About

Specification Name: Sdtrig Effective Privilege Mode
Authors: @Beeman Strong
Spec Jira: RVS-3623: Sdtrig Effective Privilege Mode (Sdtrigepm) Specification in Planning

Background

Hypervisors use HLV/HSV instructions, or load/stores with MPRV=1, when emulating operations on behalf of a guest
Sdtrig triggers match these load/store operations based on the current privilege mode, rather than the effective privilege mode
As a result, emulated load/store operations will bypass guest triggers, resulting in a virtualization hole

With Sdtrigepm, mcontrol6 triggers match based on the effective privilege mode of a load/store access
- This impacts both privilege mode filtering and breakpoint reentrancy protections

None

Proof-of Concept

Software Support (OS, RTOS, Hypervisor, etc.)

Simulator Support

Tests (ACT for ISA or Software)

ACT: ensure HLV/HSV accesses match mcontrol6 triggers enabled for VS/VU, not S/U
ACT: ensure HLVX and MPRV=MXR=1 accesses do not match mcontrol6 triggers
ACT: ensure loads/stores with MPRV=1 only match mcontrol6 triggers enabled for mode in MPP/MPV

No changes. Future hypervisor functionality to emulate loads and stores will now work properly.

Item	Description	Plan	Resources

Item	Description	Plan	Resources
Opcode	Enough opcode encoding to support GCC.	N/A	N/A
Simulator	Enough simulator support so that basic RISC-V tests can be run. See the policy for more details.	Planned - Spike & Qemu	Rivos
psABI	ABI extensions (if necessary)	N/A	N/A
GCC	Support on GCC (optimizations not required)	N/A	N/A
LLVM	Support on LLVM (optimizations not required)	N/A	N/A
RISC-V Test Input	Test configuration input (YAML schema & values, Test Coverage YAML rules, see the policy)	N/A	N/A
RISC-V Tests	Basic tests that do not cover corner cases. See the policy for more details.	Planned	Rivos
RISC-V SAIL	Enablement of the new specification/extension as part of the RISC-V SAIL Golden Model.	Planned	Rivos